148 Inspection items for PCB design -PCB checklist

148 Inspection items for PCB design -PCB checklist

1. Data input stage

1. The information received on the process is complete (Includes: schematic diagram, *.BRD file, material list, PCB design instructions and PCB design or change requirements, standardization requirements, process design documentation).

2. Verify that the PCB template is up to date

3. Confirm that the positioning device location of the template is correct

4. PCB design instructions and PCB design or change requirements, standardization requirements indicate whether it is clear

5. Verify that the keep out area and wiring areas on the profile are already reflected on the PCB template

6. Compare the outline diagram to confirm that the dimensions and tolerances of PCB are correct, and that the PTH holes and NPTH holes are defined accurately

7.It's best to lock the structure file after confirming the PCB template, to avoid misoperation

2. Post-inspection stage of layout

a. PCB components inspection

8, Verify that all components packages are consistent with the corporate consolidated library and that the package library has been updated

9, The motherboard and the sub board, the single board and the back plate, confirm the signal corresponds, the position corresponds, the connector direction and the silk print marking is correct

10, Components are 100% placed

11, Open the place-bound of the top and bottom layers of the components to see if the overlap-induced DRC allows

12, Mark Point is sufficient and necessary

13, Heavier components, should be placed near the PCB support point or support side of the place to reduce the warp of the PCB

14, Structure-related devices are best locked after the layout, prevent misoperation to move the position

15, Within 5mm range of crimping sockets, do not allow components with a height exceeding the height of the crimping socket on top, bottom don’t allow. No components or solder points are allowed on the back.

16, Determine if the device layout meets the technical requirementsFocus on BGA, PLCC and SMD sockets

17, Metal shell components, pay special attention not to collide with other components, to leave enough space position

18, Interface-related devices as close as possible to the interface placement, backplane bus driver as close to the backplane connector placement

19, Whether the chip device of wave soldering surface has been converted into wave soldering package

20, Is there more than 50 manual solder joints

21, The component on PCB which axial insertion is higher, should be considered horizontal installation

22, Components that need to use the heatsink, confirm adequate spacing with other devices, and pay attention to the height of the main device within the heatsink range

b. Function check

23, Whether the digital circuit and analog circuit device layout are separated and the signal flow is reasonable

24, A/d converter placement across modular partitions

25, Whether the clock device layout is reasonable

26, The layout of high speed signal device is reasonable

27, Whether the end device has been properly placed

28, The number and position of the decoupling capacitance of IC devices are reasonable

29, The signal line takes the plane of different level as the reference plane, when crossing the plane partition area, whether the connection capacitance between the reference plane is close to the signal line area.

30, Whether the layout of the protection circuit is reasonable and whether it is advantageous to split

31, Whether the fuse of the single board power supply is placed near the connector, and there is no circuit component in front of it

32, Confirm strong signal and weak signal (power 30dB difference) circuit separate layout

33, Whether to place devices that might impact EMC experiments according to the design guidelines. Such as: Reset circuit to slightly closer to the reset button

c. Heat dissipation

34, Heat-sensitive components (including liquid dielectric capacitance, crystal oscillator) as far as possible away from high-power components, radiators and other heat sources

35, Does the layout meet the thermal design requirements, heat dissipation channel

d. Power supply

36, IC power supply is too far away from the IC

37, Ldo and surrounding circuit layout is reasonable

38, Module power supply and other surrounding circuit layout is reasonable

39, Whether the overall layout of the power supply is reasonable

e. Rule settings

40, Whether all emulation constraints have been correctly added to constraint manager

41, Whether physical and electrical rules are set correctly

42, Test Via, test pin spacing setting is sufficient

43, Lamination thickness and solution to meet design and processing requirements

44, Whether the differential line impedance has been calculated and controlled by rules

3.Post-Inspection stage of layout

f. Digital model

45, Whether the alignment of digital circuit and analog circuit is separated and whether the signal flow is reasonable

46, If A/d, d/A and similar circuits are split, then whether the signal line between the circuits is separated from the bridge contact between the two places (difference line exception)

47, The signal line must be crossed across the gap between the power supplies to refer to the complete ground plane.

48, If the ground layer design zoning is not segmented, we should ensure that the digital signal and analog signal partition wiring.

g. The clock and the high speed section

49, The impedance of high speed signal line is consistent with each layer

50, High-speed differential signal lines and similar signal lines, whether equal length, symmetry, near parallel to the line

51, Make sure the clock line is in the inner layer as far as possible.

52, Confirm that the clock line, high speed line, reset line and other strong radiation or sensitive lines have been routed as far as possible according to the 3W principle

53, Clock, interrupt, reset signal, hundred gigabit/Gigabit Ethernet, no fork test point on high speed signal

54, Whether the LVDS and TTL/COMS signals are as satisfied as possible between 10H (H is the height of the reference plane of the signal line distance)

55, Whether the clock line and the high speed signal line avoid traversing through the dense through hole area or the device pin between the lines.

56, Whether the clock line has met (SI constraint) requirements

57, Difference pairs, high-speed signal lines, all types of bus has been met (SI constraints) requirements

h. EMC and Reliability

58, For the crystal oscillator, whether layout a ground layer in the low? Does it prevent the signal line from moving through the device pins?

59, No sharp angle and right angle on the single board signal walking line

60, For double-sided PCB, check that the high speed signal line is closely connected with its return wire. For multilayer PCB, check whether the high-speed signal line as close to the ground plane

61, For the adjacent two-layer signal lines, try to line up vertically.

62, Avoid the signal line through from the Power module, common mode inductance, transformers, filters

63, Try to avoid high-speed signal on the same layer of long-distance parallel line

64, Whether there is a shielding through hole at the edge of the PCB

65, Suppression device corresponding signal line is short and thick on the surface

66, Confirm power supply, Ground layer no island, no large open slot, no long ground plane cracks

67, Whether place the ground through hole at the place which signal line across a lot of.

i. Power and ground

68, If the power supply/ground plane has the division, as far as possible avoids splits the reference plane to have the high-speed signal crossing.

69, Confirm that the power supply and the ground can carry enough current, whether the number of holes meets the bearing requirements

70, For special requirements of the power supply, whether to meet the requirements of buck

71, To reduce the edge radiation effect of plane, 20H principle should be satisfied between the power layer and stratum

72, If there is a division, whether the divided ground does not constitute a loop

73, Does the different power plane of the adjacent layer avoid overlapping placement

74, The isolation of protected ground, -48v and GND is greater than 2mm

75, Whether the -48v is just a -48v signal reflux, not wired to other ground

76, Whether design the 10~20mm of the protective ground near the connector panel? And connecting each layer with a double row of staggered holes?

77, Whether the distance between the power line and other signal lines meets the safety requirements

(To be continued)